1. Field of the Invention
The invention relates to a method for the double sided polishing of a semiconductor wafer. In particular, the invention is intended for double sided polishing of silicon wafers in the next technology generations, primarily wafers which have a diameter of 450 mm.
2. Background Art
At present, polished or epitaxially coated silicon wafers with a diameter of 300 mm are mainly used for the most demanding applications in the electronics industry. Silicon wafers with a substrate diameter of 450 mm are in development.
An essential reason why the electronics industry desires larger substrates for the production of their components, whether microprocessors or memory chips, resides in the enormous economic advantage which they promise. In the semiconductor industry it has for a long time been customary to focus on the available substrate area, or in other words to consider how great a number of components, i.e. logic chips or memory chips, can be accommodated on an individual substrate. This is related to the fact that a multiplicity of the component manufacturer's processing steps are aimed at the entire substrate, but there are also the individual steps for structuring the substrates i.e. producing the component structures which subsequently lead to the individual chips, and therefore the production costs for both groups of processing steps are determined very particularly by the substrate size. The substrate size influences the production costs per component to a very considerable extent, and is therefore of immense economic importance.
However increasing the substrate diameter entails great and sometimes entirely new, hitherto unknown technical problems. Thus, for example, all the processing steps, whether they are purely mechanical (sawing, grinding, lapping), chemical (etching, cleaning) or chemical-mechanical in nature (polishing) as well as the thermal processes (epitaxy, annealing), require thorough revision, in part also with respect to the machines and systems (equipment) used for them.
The present invention focuses on the polishing of a semiconductor wafer as the last essential processing step when the wafer is intended for the production of memory chips, or in principle as the penultimate essential processing step which precedes epitaxy of the wafer, when the wafer is intended to be used as a so-called epi wafer for the production of modern microprocessors.
In the fabrication of semiconductor wafers, it is particularly critical to achieve a sufficiently good edge geometry in the region at a distance of less than or equal to 2 mm from the edge of the wafer, and the nanotopology.
Nanotopology is conventionally expressed as a height variation PV (“peak to valley”), based on square measurement windows with an area of 2 mm×2 mm. The term “nanotopology” or “nanotopography” is defined by SEMI (Semiconductor Equipment and Materials International) as meaning the planarization deviation of the entire wafer frontside in the spatial wavelength range of from 0.2 to 20 mm (lateral correlation length) and within the “fixed quality area” (FQA; a surface region for which the properties stipulated in the product specification must be fulfilled). The nanotopology is measured by fully scanning the entire wafer surface with measurement fields of different size and with overlap. Not one of the surface height variations (peak to valley) found in these measurement fields is allowed to exceed the maximum value required for the entire wafer. The measurement field sizes are defined specification-dependently and, for example, over 2×2 mm2, 5×5 mm2 and 10×10 mm2.
In general, the final nanotopology of a semiconductor wafer is generated by a polishing process. In order to improve the planarity of a semiconductor wafer, equipment and methods for simultaneously polishing the frontside and backside of the semiconductor wafer have been provided and further developed.
So-called double sided polishing (DSP) is described, for example, in U.S. Pat. No. 3,691,694. According to an embodiment of double sided polishing as described in EP 208315B1, semiconductor wafers in metal or plastic “carrier plates” or “templates”, which have suitably dimensioned recesses, are moved on a path predetermined by machine and process parameters between two rotating polishing plates covered with a polishing pad in the presence of a polishing sol, and are thereby polished.
The double sided polishing step is conventionally carried out with a polishing pad of homogeneous, porous polymer foam with a hardness of from 60 to 90 (Shore A), as described for example in DE 10004578C1. There, it is disclosed that the polishing pad adhering to the upper polishing plate is permeated by a network of channels and the polishing pad adhering to the lower polishing plate has a smooth surface without such a texture. This measure is intended on the one hand to ensure homogeneous distribution of the polishing agent being used during the polishing, and on the other hand to prevent the semiconductor wafer from sticking to the upper polishing pad when the upper polishing plate is lifted after polishing has been completed.
For double sided polishing, the semiconductor wafer is placed in a recess of a carrier plate so that the backside of the semiconductor wafer rests on the lower polishing plate.
Besides DSP, so-called CMP polishing is also necessary in the prior art in order to eliminate defects and reduce the surface roughness. In CMP, a softer polishing pad is used than in DSP. Furthermore only one side of the semiconductor wafer is polished by means of CMP, namely the side on which components are subsequently intended to be fabricated. The prior art also refers to this as finish polishing. CMP methods are disclosed, for example, in US 2002/0077039 and in US 2008/0305722.
WO 99/55491 A1 describes a two-stage polishing method with a first FAP (“fixed-abrasive polishing”) polishing step using a polishing pad with abrasive fixed in it, and a subsequent second CMP (“chemical-mechanical polishing”) polishing step. In CMP (as in DSP), in contrast to FAP polishing, the polishing pad contains no fixed abrasive substance. Here, as in a DSP step, abrasive substances in the form of a suspension are introduced between the silicon wafer and the polishing pad. Such a two-stage polishing method is used in particular to eliminate scratches which the FAP step has left behind on the polished surface of the substrate.
German Patent Application DE 102 007 035 266 A1 describes a method for polishing a substrate of silicon material, comprising two polishing steps of the FAP type which differ in that a polishing agent suspension which contains unbound abrasive substance as a solid is introduced between the substrate and the polishing pad in one polishing step, while in the second polishing step the polishing agent suspension is replaced by a polishing agent solution which is free of solids.
It has been found that the methods of double sided polishing followed by a finishing CMP polish, which are known in the prior art, will not meet future requirements for edge geometry and nanotopology and are unsuitable for processing wafers with substrate diameters of 450 mm. It would be highly desirable to provide such a method.